Magnetic recording of digital data is typically accomplished by recording a series of transitions, changes in direction of magnetization, the spacing of which defines the data. There are various codes which have been used to correlate the timing of the transitions with digital data.
These codes often provide for the recording of timing information so that, even in the presence of variations in the speed of the recording medium, the timing of playback signals can be correlated with the timing of the signals used to make the recording. In systems capable of recording two or more tracks in parallel, timing information can be provided in a clock track which is recorded in parallel with the track containing the data. On playback, the signal from the clock track indicates at which times the signal from the data track is to be interpretted as data.
At high recording densities it can be difficult to obtain the necessary timing alignment between the clock and data tracks. For this and other reasons, codes have been developed which mix data and clock information on a single track.
One such code, a form of frequency modulation (FM), combines data and clock as follows: a bitcell is the time allocated to encoding of a single data bit; the first half of each each bitcell is a data window, the second half is a clock window; if the data associated with a bitcell is a 1, then there is a transition in the center of the data window, otherwise there is no transition in the data window; there is always a transition in the clock window. In this FM code there is guaranteed to be a transition at the same place in every bitcell (in the middle of the clock window); this fact makes extracting timing information from the combined clock and data signal relatively easy.
A modified version of this FM code (MFM) has been developed in which some of the clock transitions are not written. The minimum distance between recorded transitions is one of the primary factors determining how much data can be recorded on a particular tape or disk. Thus MFM enabled recording at higher data densities than FM. This higher recording density is obtained at the cost of making the clock information more difficult to extract from the MFM signal. This is because in MFM there is no one time within a bitcell in which a transition is guaranteed to occur; in fact, there may be bitcells with no transition at all.
To decode an MFM signal it is necessary to reconstruct the clock signal to get not just the width of the bitcells, but also to get the phase information necessary to identify that portion of the bitcell in which data transitions are to occur that is, the data window. This reconstruction must be accomplished from a mixture of clock and data transitions which occur in an unpredictable mixture which depends on the data which has been encoded.
Phase-locked loops (PLL) have been applied to the task of reconstructing clock signals from MFM signals, but difficulties have been encountered. Data is typically recorded in blocks, between which is a gap without transitions. It is necessary to synchronize at the beginning of each block. One problem experienced with some PLL designs is that during this synchronization period, they can lock to harmonics or beat frequencies, rather than to the bit rate. Another problem is that some PLLs lock slowly, so that if the PPL's frequency at the beginning of the synchronization period is too different from the bit rate, the PLL will not have locked by the end of the synchronization period.
A PLL includes a voltage-controlled oscillator (VCO), the frequency control of which is driven by the loop error signal. A VCO has a limited frequency range over which it can be driven. A larger range can help a PLL lock more quickly and (for loops subject to locking to a harmonic or beat frequency) can make it less likely that the loop will lock to a harmonic or beat frequency.
If the PLL locks to a frequency that is near one of the ends of the frequency range of the VCO, then the extent which the VCO can be driven in that direction is limited. Thus, it is desirable to have the center of the VCO's range correspond to the frequency at which the PLL is locked. Two factors contribute to the difficulty in obtaining this objective: (1) variations in component values create variations in the VCO center frequency among different instances of the same VCO design; (2) variations in other parts of the system (for example, variations in tape speed) can make it impossible to expect the PLL to lock one predetermined frequency. The first source of difficulty can be overcome by providing a trim adjustment; however, this increases the cost of the product by requiring each product to be individually adjusted.